Clock tree synthesis for low power consumption and low clock skew

ABSTRACT

A method for low power clock tree synthesis using buffer insertion, removal and resizing for high-speed VLSI design is proposed. The developed tool can be embedded in the existing clock tree synthesis design flow to ensure satisfying both the specifying database constrains and the clock skew constrains. For a given clock tree netlist, the location information of buffers, the parameters of wires and the buffers&#39; timing and power library are all included. The buffer delay and wire delay of the clock tree are calculated first. Then the feasible solution is solved if the input netlist is not feasible for the given constrains. Finally, a modified low power clock tree netlist, which satisfies the timing specifications, is obtained using our proposed method.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a clock tree synthesis, and more particularly to a clock tree synthesis for low power consumption and low clock skew.

2. Description of Related Art

In the modern high speed VLSI design era, clock design plays a crucial role in determining chip performance and facilitating timing and design convergence. The clock routing is important in the layout design of synchronous digital system as it influences the correctness, area, speed and power dissipation of the synthesized system [reference 1 and 2]. The drastically increased requirement for high performance and high speed VLSI circuits has posed challenges to the design of high speed clock network, where clock delay and skew minimization has been a critical problem. So some circuit designers' inclination is toward developing techniques to minimize the power dissipation, clock latency and clock skew well developed, understood design and verification flows.

Buffer operations are widely used in designing clock distributed network [reference 3]. The buffers can decouple the capacitance to reduce the equivalent loading of each wire, so the rise time and wire delay could be reduced. Also when the signal's transfer time is faster, it can reduce the power consumption. Several methodologies is adopted in power and clock skew minimization. The previous research inserts the buffers and constructs H-tree to reach the optimization solution in both area and power consumption aspect [reference 4]. The balanced buffer insertion scheme attempts to partition the clock tree into several subtrees such that every subtree has equal path length and all source-to-sink paths have an equal number of levels. Clock gating is another well-known technique in reducing the dynamic power dissipation of a digital circuit [reference 5 and 6]. It saves power by shutting off the sequential elements and part of the clock network during the idle state.

The design of the clock distribution network also determines the clock skew. Clock skew directly affects chip performance in a close to one-to-one ratio since it has to be counted as cycletime penalty. The clock trees need to be incrementally adjusted accordingly with minimum changes to ensure acceptable clock skew. Buffer insertion usually deals with clock skew minimization problem [reference 7, 8 and 9]. Other research using buffer insertion method minimizes both power consumption and clock skew criterion [reference 4, 10].

SUMMARY OF THE INVENTION

The main objective of the present invention is to provide an improved clock tree synthesis that reduces the power consumption and clock skew of the clock skew.

To achieve the objective, the clock tree synthesis in accordance with the present invention can be embedded in the existing clock tree synthesis design flow to ensure satisfying both the specifying database constrains and the clock skew constrains. For a given clock tree netlist, the location information of buffers, the parameters of wires and the buffers' timing and power library are all included. The buffer delay and wire delay of the clock tree are calculated first. Then the feasible solution is solved if the input netlist is not feasible for the given constrains. Finally, a modified low power clock tree netlist, which satisfies the timing specifications, is obtained using our proposed method.

Further benefits and advantages of the present invention will become apparent after a careful reading of the detailed description with appropriate reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a design flow chart of the clock tree synthesis in accordance with the present invention;

FIG. 2 is a diagrammatic sketch of power consumption for the three levels clock tree design;

FIG. 3 is a reduced standard parasitic format interconnect of the present invention;

FIG. 4 is a pseudocode of the simulated annealing based optimization algorithm; and

FIG. 5 is a pseudocode of the simulated annealing algorithm.

DETAILED DESCRIPTION OF THE INVENTION

A clock distribution network that has been implemented with a cell placement and an initial clock tree is given. And a specified liberty library that includes clock buffers and D-flip-flops (DFF) is also given. We wish to design a clock network to dissipate minimal power and satisfy clock skew constraint at all receivers (DFFs). The clock skew should be small, even under process variations. The developed software has to apply allowable techniques, such as buffer insertion, buffer resizing, and buffer removal to reduce the dynamic power under the constraint of the maximum clock skew. It is allowed to resynthesize a better clock tree, except that the root of the clock tree should be the same as the root of the initial clock tree.

The power dissipated by a clock distribution network can be attributed to the charging and discharging of the wiring and load capacitances through the interconnect resistance and driver resistance and to the static power dissipated, if any, by the buffers P=P _(static) +P _(dynamic) =ΣP _(i) +C _(o) ·L(T)·f·V ²   (1) Here, P_(i) is the static power dissipated by the ith clocked components. C_(o) is the capacitance per unit length and is set to 0.000076 in practical experience. L(I) is the wire length of the tree and can be simplified to Manhattan distance, L(T)=|X _(cell1) −X _(cell2) |+|Y _(cell1) −Y _(cells)|  (2)

-   -   where X_(cell1) and X_(cell2) are the physical coordinate of         cell_(i). f and V are the frequency of operation and the voltage         swing, respectively.

The clock network design determines the buffer sizes, their locations, and the interconnect topology. It therefore affects the summation in the first term and the wire length in the second term. In Eq. 1, the static power of each gate is defined in the power model of specified library. Both rise power and fall power have to be considered in a clock cycle. For CMOS VLSI, the static power consumed by the buffers is negligible, so that the problem reduces to one of minimizing the total capacitance, which is contributed by both wiring and buffers. In ECL, the static power dissipated by the buffers dominates. For multichip modules, both dynamic and static power consumption maybe equally important.

Considering the clock skew constraint, the ithe cell's clock latency can be represented as t_(cd) ^(i). For a zero clock skew clock tree designs, the clocked component ∀(i,j)∈T, s.t. t _(cd) ^(i) =t _(cd) ^(i)   (3) In a digital synchronous circuit, the clock skew T_(Skew)(i,j) between the registers R_(i) and R_(j) is defined as the algebraic difference, T _(Skew)(i,j)=t _(cd) ^(i) −t _(cd) ^(j)   (4) According to the characteristic of clock network, the clock tree design considers only the clock latency from clock root to the sink without thinking about the physical routing path.

In this clock distribution network design problem, we also consider the design rules constaints (DRC) problem, including the input signal transition time and output loading constraints. The input transition time constraints can be defined as ∀_(i)∈T, s.t. T^(i)≦T_(k),   (5) where T_(k) is the specified maximum allowed input transition time of k-type cell, and T^(i) is the transition time of the signal at the ith sink. Note that this constraint is extremely important as any recognizable clock must have a clock period of at least three times the 10%-to-90% rise time. The rise time of classically designed clock nets imposes a limit on the frequency of operation, even if logic delays are small.

In this section, we will introduce our proposed clock tree synthesis tool for both low power consumption and low clock skew using buffer insertion, removal and resizing operations. Depending on different technology library, our proposed method could adopts various adjustment for the constraints. The pseudocode of the design flow is shown in FIG. 1. First, our proposed method loads three input files, including the original clock tree design, technology depended buffer and DFF library, and the constraint of optimization target. Second, the program checks that whether the original design meets the constraint or not. If there is a DRC violation condition, the program will modify it and conquer it. Third, a fast buffer resizing operation is executed to decrease the entire power consumption, but it takes risks to violate the design constraint. So the program checks the design again to avoid the unwanted condition in the next step. Finally, a simulated annealing (SA) algorithm based optimization method is hold to reduce the power consumption and clock skew of the clock tree. The detailed procedure is shown below.

In the procedure of low power consumption in clock tree syntheses, our proposed method provides different methodology depending on different technology library. In the speci-fied buffer library, for instance, CLKBUFXL is the smallest size and CLKBUFX20 is the largest. For example, a simple three levels clock tree contains 100 DFFs in the leaves and buffer CLKBUFX8 in the root node. The power consumption of the clock tree is shown in FIG. 2. The X axes means the number of buffer in the second level of the clock tree. If there is only one buffer, then the buffer should connect to all of the 100 DFFs; if there are two buffers, then each buffer should connect to 50 DFFs in average. The Y axes means the type of the buffer, the index from 1 to 9 means CLKBUFXL, CLKBUFX1, CLKBUFX2, CLKBUFX3, CLKBUFX4, CLKBUFX8, CLKBUFX12, CLKBUFX16 and CLKBUFX20, respectively. The zero power consumption means that there is a DRC violation condition in the input transition time or the output loading constraints. According to the power distribution in FIG. 2, we observe that CLKBUFX8 is the best choice in the fast buffer operation.

The timing constraint is depended on the propagation delay from the root buffer to the DFF leaf in the clock tree. It also means the summation of buffer internal delay and interconnect delay on the entire path, such as $\begin{matrix} {t_{cd}^{i} = {{\sum\limits_{j \in {P\quad{(i)}}}\quad{BUF}_{j}} + {\sum\limits_{k \in {P\quad{(i)}}}\quad{wire}_{k}}}} & (6) \end{matrix}$ where P(i) is the path from root node to the ith buffer, BUF_(j) means the internal delay of the jth buffer on the path P(i), and wire_(k) is the kth interconnect on the path P(i). In order to calculate the propagation delay quickly, the parameter of interconnects can be simplified as reduced standard parasitic format (RSPF). In this model, the buffer resizing will not affect the interconnect delay. FIG. 3(a) shows the parasitic model between buffer A and B, and the transfer function is represented as Y(s). FIG. 3(b) is the parameter of RSPF model, where the p-model (R1, C1 and C2) is the approximation of the first three orders of Y(s). It also means the equivalent loading of buffer A, the value is C1+C2. The pin-to-pin interconnect delay can be simply shown in RC model, the value is R2×C3.

In order to simplify the computational cost, we choose the wire loading as direct proportion of physical length. And only considering the relationship between delay of buffers and its loading, and neglecting the effects of interconnect delay. In other words, the buffers or DFFs connect to the same driving buffer have the same input transition time and the same clock latency. The buffer's internal delay and output transition time uses the table look-up method from the specified library. If there is not exact value in the look-up table, the interpolation method is used instead. Generally speaking, the DFFs often connect in the leaf node and the number of DFFs is more than ten times of the number of buffers in a clock tree design.

In this subsection, we will show the benefit of buffer operation for low power consumption and low clock skew constraint. In order to meet the low clock skew constraints in the clock tree, we try to move all of the DFFs to the leaves nodes according to the output loading of the connected buffer. The loading of the buffer will affect both its internal delay and its output clock transition time, which is also the input clock transition time of the next components. The large input clock transition time will cause both the large power consumption and large internal delay. So the balanced output load of buffers is the target to reduce both power consumption and clock latency.

In the fast feasible solution operation, the operation of buffer removal and resizing is applied. In the condition of improved performance, the buffers in the common path could be removed for reducing the power consumption. Next, according to the output loading of leaves, our program changes the buffer size to the minimal requirement and calculates the total power consumption. Then the proposed method changes all buffers to the same type to decrease the power rapidly. Finally it chooses one suitable buffers set if it exists.

In this subsection, it can be guarantee that there is no DRC violations in the clock distributed network design when entering this procedure. The pseudocode of optimization flow is shown in FIG. 4. The heuristic procedure first disturbs the distribution of a few DFFs. Then the program checks whether the total power consumption increases or not. If the worse result is appeared, then the algorithm will reset the distribution of DFFs to the previous status. In the simulated annealing algorithm procedure, shown in FIG. 5, a temperature coefficient T is introduced and a cooling factor α=0.9 is used. The cost of changing is defined as Δc=cos t(prev)−cos t(opt), the acceptable probability of changing is e^(−Δc/T) , and the new temperature T is defined as α T.

In order to reduce the computational complexity, we choose the DFFs in the same level of the clock tree to vary at the same time. It is reliable that the clock skew could be reduced simultaneously. After the simulated annealing procedure, the program checks the power consumption again. If there is improvement then the program try to disturb the distribution of DFFs again and repeat the procedures above. Else if there is no improvement, the program resets the clock tree structure to the previous status and is terminated.

We implemented our proposed method in C on a SUN Blade 2000 with gcc 2.95 compiler. To illustrate the accuracy and efficiency of the proposed method, five test cases of clock tree design were provided for comparison studies. The information of each test case was shown in Table I, including the number of buffers, the number of DFFs, the power consumption, the maximum clock latency and the clock skew of the original clock tree design. After applying the proposed method, the information of maximum clock latency and power consumption of the specified test cases under different clock skew constraint was shown in Table II. The result of optimization operation of the clock tree was shown in FIG. 6, the maximum and the minimum clock latency were highlighted on the figure. It was shown in Table II that our method could decrease the power consumption to 10% in average for a feasible solution, such as Exam. 1. Furthermore, we could intensify the clock skew constraint. We could observe that although the decreasing percentage was smaller, the power consumption of optimization clock tree design was still smaller than the original one. It was also shown in Table II that the maximum clock latency increases in some cases. It was caused by the buffer inserting operation during the balanced clock tree structure. However, the increasing of both maximum clock latency and the minimum clock latency, it was not matter to the operation of clock tree.

We have proposed a clock tree synthesis tool to perform buffer insertion, removal, resizing simultaneously for low power consumption and clock skew minimization in digital synchronous circuit design. Based on the traditional circuit design flow, our method considers different specified technology libraries to satisfy the design objective. Using the simulated annealing based optimization algorithm, our method can reduce more than 10% of power consumption comparing to the original design in average. Experimental results have demonstrated the accuracy and the efficiency of the proposal method.

Although the invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed. TABLE I COMPARISONS OF THE FIVE TEST CASES Case 1 Case 2 Case 3 Case 4 Case 5 Number of 30 113 251 238 262 Buffer Number of 500 1234 5000 5000 500 DFF Power 21.461 52.056 210.505 214.551 214.513 Consumption (mW) Max. Clock 0.874 1.130 1.214 1.224 1.223 Latency (ns) Clock Skew 0.014 0.020 0.055 0.064 0.060 (ns)

TABLE II OPTIMIZATION RESULTS ANALYSIS Case 1 Case 2 Case 3 Case 4 Case 5 Exam. 1 Clock Skew Constraint(ns) 0.08 0.1 0.5 0.5 0.5 Max clock Latency Increase +40% +54% +124%  +104%  +43% Power Consumption(mW) 18.014 44.323 189.736 197.257 193.030 Power Reduced(%) 16.06 14.86 9.87 8.06 10.01 Exam. 2 Clock Skew Constraint(ns) 0.02 0.05 0.1 0.1 0.1 Max clock Latency Increase −12% +14% +33% +48% +11% Power Consumption(mW) 18.728 45.038 192.383 196.944 197.983 Power Reduced(%) 12.73 13.48 8.60 8.2 7.59 Exam. 3 Clock Skew Constraint(ns) 0.01 0.02 0.05 0.08 0.07 Max clock Latency Increase  +1%  +7% +14% +37%  +8% Power Consumption(mW) 19.858 51.434 195.837 204.858 207.403 Power Reduced(%) 7.47 1.19 6.96 4.51 3.31 Exam. 4 Clock Skew Constraint(ns) 0.005 0.015 0.03 0.06 0.05 Max clock Latency Increase  −6%  +4%  +4% +46%  +7% Power Consumption(mW) 21.394 51.723 204.903 200.482 209.710 Power Reduced(%) 0.31 0.64 2.66 6.55 2.2

REFERENCES

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1. A clock tree synthesis for low power consumption and low clock skew, comprising the steps of: inputting clock tree synthesis netlist including the electric parameter data of each of paths, timing of buffers and the power database; inputting the timing standard maximum of clock skew; determining the buffers according to the design standard via a design standard validator that calculates the signal inputting to the root of clock tree to each buffers, the transfer time of flip-flop and the output load of each buffer; balancing the clock tree load, and solving the conditions of departing from the specific database design standard and the clock tree skew greater than that of the design standard; changing the type of the buffer for quickly searching a feasible solution for reducing the power consumption of the clock tree; and using heuristic of the specific database and the processes of optimum based on simulating annealing method for searching the interconnect of the buffer on the clock tree to gain a optimization solution of the power consumption of the clock tree in all areas.
 2. The clock tree synthesis as claimed in claim 1, wherein the design standard validator executes the steps of determining the transfer time of the input signals according to the characteristics of the buffers; determining the output load of the buffers according to the characteristics of the buffers; and using the transfer time of the output signals, output load and interpolation method to calculate the clock delay of the buffers and the transfer time of the output signal.
 3. The clock tree synthesis as claimed in claim 1, wherein balancing the clock tree load comprises the steps of: connecting all the flip-flops to the last layer of the clock tree, and re-connecting according to the load balance of the buffers for reducing the influence of the clock skew on the clock tree; balancing the output load of the buffers of the last layer of the clock tree for reducing the clock skew and minimizing the whole clock delay; and the clock delay of the buffers in the clock tree seriously influencing the whole clock skew such that to balance the output load of the buffers can effectively solve the limit of the clock skew and improve the signal transfer time for reducing the power consumption of the clock tree. 